Semiconductor memory device is classified into a cell array portion and a peripheral circuit portion. The cell array portion has a plurality of unit cells which are arranged in the form of matrix, so as to store data in the unit cells. The peripheral circuit portion is provided to drive the unit cells and is located at the outside of the cell array portion. In general, a unit cell of DRAM device is comprised of one transistor and one capacitor, while the peripheral circuit thereof is comprised of a plurality of circuit components, for instance, various types of transistors and a large number of resistors.
When a semiconductor memory device is fabricated, the cell array and peripheral circuit portions are nearly formed at the same time. Thus, some semiconductor material used to form the cell array portion may be sometimes used to form the circuit components constituting the peripheral circuit portion.
FIG. 1A and 1B show the construction of a prior art DRAM device. FIG. 1A shows, by a cross-sectional representation, a portion of cell array portion of the prior art DRAM device, and FIG. 1B shows, by a cross-sectional representation, a portion of peripheral circuit portion thereof. In this prior art DRAM device, a resistor 29 is made of the same semiconductor material that a bit line 28 is made of. From these figures, reference numeral 10 denotes a semiconductor substrate, numeral 12 denotes a field oxide layer, numeral 14 denotes a source region, numeral 16 denotes a drain region, numeral 18 denotes a gate electrode, numeral 20 denotes an insulation layer for electrically insulating the gate electrode 18 from other conductive layers, numeral 22 denotes a first pad layer for connecting a storage electrode and the source region 14, numeral 24 denotes a second pad layer for connecting a bit line and the drain region 16, numeral 26 denotes an inter-layer insulating layer, numeral 28 denotes a bit line, and numeral 29 denotes a resistor.
The bit line 28 is, as shown in FIG. 1A, comprised of two layers, one of which is a polysilicon layer 28a and the other is a silicide layer 28b formed on the polysilicon layer 28a. Also, the resistor 29 has a polysilicon layer 29a and the other is a silicide layer 29b formed on the polysilicon layer 29a, as shown in FIG. 1B.
In an effort to enhance the integration degree and operation speed of a semiconductor memory device, a polycide structure comprised of overlapped polysilicon and silicide layers has been mostly used to form a gate electrode, as compared with a single polysilicon structure. This is because resistance of the gate electrode can be reduced owing to less sheet resistance of the silicide layer. The sheet resistance (Rs) of the polycide may be varied, depending on the thickness and specific resistance of the polycide but in general, is quite small level of about 2.about.20 .OMEGA./.quadrature..
As illustrated in FIG. 1B, therefore, in order to form the resistor of the memory device using the gate electrode-forming material (i.e., polycide), the length of the resistor's should be sufficiently extended.
When polycide is intended for using it as the resistor, a larger area occupied by the resistor should be required owing to the above reason but if this is the case, such larger occupation may affect the integration degree of a semiconductor memory device and malfunction of the memory device may occur due to undesirable parasitic capacitance among various conductive layers.
FIG. 2A and FIG. 2B show, by cross-sectional representations, the construction of another prior art DRAM device. FIG. 2A shows, by a cross-sectional representation, a portion of cell array portion of another prior art DRAM device, and FIG. 2B shows, by a cross-sectional representation, a portion of peripheral circuit portion thereof. In this prior art DRAM device, In this DRAM device, a resistor 35 is made of the same semiconductor material that a storage electrode 34 is made of. From these figures, reference numeral 30 denotes an etch-stopper layer, numeral 32 denotes an insulating layer, numeral 34 denotes a storage electrode, and numeral 35 denotes the resistor. Of undescribed numerals of FIGS. 2A and 2B, the same reference numerals as those of FIGS. 1A and 1B denote the same portions, respectively.
The resistor 35 has the same structure as that of the storage electrode 34, as shown by cylindrical shapes of FIG. 2A and FIG. 2B. This is because a process of forming the storage electrode is simultaneously performed at both cell array portion and peripheral circuit portion. That is, the resistor 35 is formed during the formation of the storage electrode 34, and thus it resembles a shape of the storage electrode.
With the increase of the integration degree of semiconductor memory devices, a capacitor constituting a unit cell has been formed in a three-dimensional structure, e.g., cylindrical, pin, and crown shapes. When the resistor is formed in a three-dimensional structure, polysilicon having somewhat high sheet resistance is employed as the storage electrode-forming material. However, such material has recognized some disadvantages as follows:
a) Since there exists a big deviation in sheet resistance (Rs) due to the process steps, desired resistance value may not be easily obtained.
b) It is not easy to form a contact window for electrically connecting a metal layer and the resistor with each other.
Under such circumstances, there is a need to overcome the above mentioned problems in fabricating a semiconductor memory device with a bit line which is made of polycide.